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PWR-82330
SMART POWER 3-PHASE MOTOR DRIVE
DESCRIPTION
The PWR-82330 is a smart Power 3phase Motor Drive Hybrid. The PWR82330 uses a MOSFET output stage with a 100 Vdc rating, and can deliver 5 A continuous, 10 A peak current to the load. This new Smart Power Motor Drive has CMOS Schmitt trigger inputs for high noise immunity. High and low-side input logic signals are XOR'd in each phase to prevent simultaneous turn on of in-line transistors, thus eliminating a shoot through condition. The internal logic controls the high and low-side gate drivers for each phase and can operate from +5 to +15 V logic levels. The internal charge pump circuitry provides the required voltage to high-side gate drives. This provides constant output performance for switching frequencies from dc to 50 kHz.
APPLICATIONS
Packaged in a small case, these hybrids are an excellent choice for high performance, high-reliability motor drives for Military and Aerospace servoamps and speed controls. Among the many applications are robotics; electro-mechanical valve assemblies; actuator systems; antenna and radar positioning; fan and blower motors for environmental conditioning; position control of mini-subs, drones, and RPV's; and compressor motors for cryogenic coolers. The PWR-82330 hybrid is ideal for harsh military environments where shock, vibration, and temperature extremes are evident, such as missile applications including fin actuators and I.R. seeker head movement. The PWR82330 operates over the -55C to +125C temperature range and is available with military processing.
FEATURES
* Small size (2.6" x 1.4" x 0.25") * 100 Vdc Rating * 5 A Continuous, 10 A peak
Capability
* High-Efficiency MOSFET Drive
Stage
* Direct Drive from Commutation
Logic
* Six Step Trapezoidal or
Sinusoidal Drive
* Four Quadrant Operation * Military Processing Available
+CAP 48 50 4
GND -CAP V+
CHARGE PUMP
VCC A VO A DRIVE A VSS A 46
5,18,19 6 8 10
VLPI VUA VLA
43,44,45
40,41,42 39
14 16
VUB VLB
DIGITAL CONTROL AND PROTECTION CIRCUITRY
VCC B VO B
36,37,38
DRIVE B
VSS B 33,34,35 32
21 23
VUC VLC
VCC C VO C DRIVE C
29,30,31
12
VSd
VSS C
26,27,28
FIGURE 1. PWR-82330 BLOCK DIAGRAM (c)
1992, 1999 Data Device Corporation
NOTES
2
TABLE 1. PWR-82330 ABSOLUTE MAXIMUM RATINGS (Tc = +25C Unless Otherwise Specified) PARAMETER SUPPLY VOLTAGE INPUT VOLTAGE LOGIC POWER-IN VOLTAGE INPUT LOGIC VOLTAGE OUTPUT CURRENT CONTINUOUS PEAK OPERATING FREQUENCY CASE OPERATING TEMPERATURE CASE STORAGE TEMPERATURE RANGE SYMBOL VCC V+ VLPI VU, VL, VSd VALUE 100 18 18 VLPI + 0.5 UNITS V V V V
lO IP fO TC TCS
5 10 50 -55 to +125 -55 to +150
A A kHz C C
PARAMETER OUTPUT Output Current Continuous Supply Voltage Output On-Resistance (each FET) Instant Forward Voltage (intrinsic diode) Reverse Recovery Time (intrinsic diode) Reverse Leakage Current INPUT POWER Input Voltage (TC=-55C to +125C) Logic Power-in Voltage V+ Current Logic Power Input Current INPUT SIGNALS (See Figure 3) Positive Trigger Threshold Voltage Negative Trigger Threshold Voltage Hysteresis Voltage Positive Trigger Threshold Voltage Negative Trigger Threshold Voltage Hysteresis Voltage SWITCHING CHARACTERISTICS ( see FIGURE 2) Upper Drive: Turn-on Propagation Delay Turn-off Propagation Delay Shut-down Propagation Delay (see FIGURE 5) Turn-on Rise Time Turn-off Fall Time Lower Drive: Turn-on Propagation Delay Turn-off Propagation Delay Shut-down Propagation Delay (see FIGURE 5) Turn-on Rise Time Turn-off Fall Time SWITCHING CHARACTERISTICS ( see FIGURE 2) Upper Drive: Turn-on Propagation Delay Turn-off Propagation Delay Shut-down Propagation Delay (see FIGURE 5) Turn-on Rise Time Turn-off Fall Time
TABLE 2. PWR-82330 SPECIFICATIONS (TC=+25C Unless Otherwise Specified) SYMBOL TEST CONDITIONS IO VCC RON VF trr Ir V+ VLPI I+ ILPI VP VN VH VP VN VH
MIN
TYP
MAX 5 100 0.13 1.25 500 250 18 18 150 5 12.9
UNIT A V V nsec A V V mA mA V V V V V V
see note 1 Ip=5A (see note 2) Ip=5A (see note 2) Id=1A, did/dt=160A/s see note 3 12 5 V+ = 15V VLPI = 15 V Pin Connections VLPI = 15 V VLPI = 15 V VLPI = 15 V VLPI = 5 V VLPI = 5 V VLPI = 5 V Test 1 Conditions VLPI = 15 V V+ = 15 V VCC = +28 V Ip = 10 A
28
160
15
2.1 1.6 0.9 0.3
10.8 4.3 3.6
td(on) td(off) tsd tr tf
825 1100 1000 125 200
nsec nsec nsec nsec nsec
td(on) td(off) tsd tr tf Test 2 Conditions VLPI = 5 V V+ = 15 V VCC = +28 V Ip = 10 A
825 1100 1000 200 200
nsec nsec nsec nsec nsec
td(on) td(off) tsd tr tf
1150 1400 1050 125 225
nsec nsec nsec nsec nsec
3
TABLE 2. PWR-82330 SPECIFICATIONS (continued) (TC= +25C Unless Otherwise Specified) PARAMETER SWITCHING CHARACTERISTICS (continued) Lower Drive: Turn-on Propagation Delay Turn-off Propagation Delay Shut-down Propagation Delay (see FIGURE 5.) Turn-on Rise Time Turn-off Fall Time DEAD TIME MINIMUM PULSE WIDTH THERMAL Maximum thermal Resistance Junction Temperature Range Case Operating Temperature Case Storage Temperature WEIGHT NOTES: 1. For Hi-Rel applications, derating per MIL-S-19500 should be observed. (Derate VCC by 70%.) 2. Pulse Width 300 s, duty cycle 2% 3. VCC = 70 V, VU, VL, = logic `0' SYMBOL TEST CONDITIONS Test 2 Conditions VLPI = 5 V V+ = 15 V VCC = +28 V Ip = 10 A MIN TYP MAX UNITS
td(on) td(off) tsd tr tf tdt tpw jc Tj TCO TCS
1150 1400 1050 125 225 400 150 7.5 150 125 150 1.37 (39)
nsec nsec nsec nsec nsec nsec nsec C/W C C C 0z (g)
each transistor
-55 -55 -55
INTRODUCTION
The 3-phase PWR-82330 is a 5 A motor drive hybrid which incorporates a 100 Vdc MOSFET output stage for high-speed and highefficiency operation. This motor drive is ideal for use in high-performance motion control systems, servo amplifiers, and motor speed control designs. Furthermore, Multi-axis systems requiring multiple drive stages can benefit from the small size of this power drive. The PWR-82330 can be driven directly from commutation logic, DSP, or a custom ASIC that supplies digital signals to control the upper and lower transistors of each phase. This highly integrated drive stage has schmitt trigger digital inputs that control the high and low side of each phase. Digital protection of each phase eliminates an in-line firing condition, by preventing simultaneous turn-on of both the upper and lower transistors. The
logic controls the high and low-side gate drivers. Operation from 5 to 15 V logic levels can be programmed by applying the appropriate voltage to pin 6 (VLPI). The PWR-82330 has a ground referenced low-side gate drive. An internal charge pump circuit supplies the required drive voltage to each of the three high-side transistors. This provides a continuous high-side gate drive even during a motor stall. The high and low-side gate drivers control the N-channel MOSFET output stage. The MOSFETs used in the PWR-82330 allow output switching up to 50 kHz. The PWR82330 does not have an internal short-circuit or overcurrent protection, which if required, must be added externally to the hybrid.
DIGITALLY CONTROLLED INPUTS
The PWR-82330 uses the Schmitt triggered digital inputs (with hysteresis) to ensure high noise immunity. The trigger switches at different points for positive and negative going signals. Hysteresis voltage (VH) is the difference between the positive going voltage (VP) and the negative going voltage (VN) (see FIGURE 3). The digital inputs have programmable logic levels, which allows the hybrid to be used with different types of commutation logic with an input voltage range of 5-15 V, such as TTL or CMOS logic. Pin 6 is the logic power input (VLPI) for the digital circuitry inside the hybrid. A 0.01 F, 50 V ceramic capacitor must be placed between this pin (6) and GND as close to the hybrid as possible. When using 15 V control circuitry, an external +15 Vdc power supply must be connected between pin 6 of the hybrid, and GND. The commutation / control circuitry can be as simple as discrete logic with PWM, or as sophisticated as a microprocessor or custom ASIC, depending on the system requirements. FIGURE 4 illustrates a typical interface of the PWR-82330 with a motor and commutation logic in a Servo-Amp System. (Refer to AN/H-3 application note for more details.)
INPUTS:
50%
tr OUTPUTS: tf
90%
50%
10%
t d (ON)
t d (OFF)
(REFERENCE TABLE 2. ALSO)
FIGURE 2. INPUT/OUTPUT TIMING RELATIONSHIPS
4
SHUT-DOWN INPUT (VSd)
Pin 12 (Vsd) provides a digital shut-down input, which allows the user to completely turn-off both the upper and lower-output transistors in all 3 phases. Application of a logic `1' to the VSd input will latch the Digital Control / Protection circuitry thereby turning off all output transistors. The Digital Control/Protection circuitry remains latched in the off state and will not respond to signals on the VL or VU inputs while the VSd has a logic `1' applied. When the user or the sense circuitry (as in FIGURE 6) returns the VSd input to a logic `0', and then the user sets the VL and VU inputs to a logic `0' the output of the Digital Control / Protection circuitry will clear the internal latch. When the next rising edge (see FIGURE 5) occurs on the VL or VU digital inputs, the outputs transistors will respond to the corresponding digital input. This feature can be used with external current limit or temperature
sense circuitry to disable the drive if a fault condition occurs (see FIGURE 6).
INTERNAL PROTECTION CIRCUITRY
The hybrid contains digital protection circuitry, which prevents inline transistors from conducting simultaneously. This, in effect, would short circuit the power supply and would damage the output stage of the hybrid. The circuitry allows only proper input signal patterns to cause output conduction. TABLE 3 lists the input/ output timing relationships. If an improper input requested that the upper and lower transistors of the same phase conduct together, the output would be a high impedance until removal of the illegal code from the input of the PWR-82330. A dead time of 400 nsec minimum should still be maintained between
1
2
V
v VH VO
N
vp
FIGURE 3. HYSTERESIS DEFINITION AND CHARACTERISTICS
+15V
+
+CAP -CAP V+ GND VLPI VUA VLA
+28V CHARGE PUMP VCC A
VO A
DRIVE A
VSS A VCC B
POSITION COMMAND HALL EFFECT DEVICES TANT + MOTOR
POSITION LOOP AND COMMUTATION LOGIC
VUB VLB
DIGITAL CONTROL AND PROTECTION CIRCUITRY
VO B
DRIVE B
VSS B VCC C
VUC
VLC
DRIVE C
VO C
VSd
PWR-82330
VSS C
FIGURE 4. TYPICAL INTERFACE WITH A MOTOR AND COMMUTATION LOGIC
5
TABLE 3. INPUT/OUTPUT TRUTH TABLE INPUTS OUTPUTS UPPERS LOWERS CONTROL VUA VUB VUC VLA VLB VLC VSd VOA VOB VOC 1 0 0 0 1 0 0 H L Z 1 0 0 0 0 1 0 H Z L 0 1 0 0 0 1 0 Z H L 0 1 0 1 0 0 0 L H Z 0 0 1 1 0 0 0 L Z H 0 0 1 0 1 0 0 Z L H 0 0 1 1 1 0 0 L L H 0 1 0 1 0 1 0 L H L 0 1 1 1 0 0 0 L H H 1 0 0 0 1 1 0 H L L 1 0 1 0 1 0 0 H L H 1 1 0 0 0 1 0 H H L 0 0 0 0 0 0 0 Z Z Z 0 0 0 1 1 1 0 L L L 1 1 1 0 0 0 0 H H H X X X X X X 1 Z Z Z H = High Level, L= Low Level, X=Irrelevant, Z= High Impedance (OFF)
PWR-82330 POWER DISSIPATION (SEE FIGURE 7)
There are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and intrinsic diode losses. VCC = +28 V (Bus Voltage) IoA = 3 A, IOB = 7 A (see FIGURE 7) ton = 20 s, T = 40 s (period) (see FIGURE 7) Ron = 0.13 (on-resistance, see TABLE 2, Io = 5 A, Tc=+25C) ts1 = 325 ns, ts2 = 325 ns (see FIGURE 7) fo = 25 kHz (switching frequency) VF is an intrinsic diode forward voltage, TABLE 2, Io = 5 A 1. Conduction Losses (PC) Pc = ( Imotor rms)2 x Ron
the signals at the VU and VL pins; this ensures the complete turn-off of any transistor before turning on its associated in-line transistor.
I motor rms =
IOB - IOB (IOB - IOA) +
2
(IOB - IOA) 3
2
ton T
CHARGE PUMP
The PWR-82330 has an internal charge pump circuit to generate the drive voltage for the high side N-channel MOSFETs. The charge pump uses an oscillator to charge an external charge pump capacitor, Cc, from the Vcc supply. This oscillator will pump the voltage at pin 48 (+cap) of the hybrid higher than Vcc. The hybrid high side drivers use this voltage to ensure the proper gate drive. An external 1 F, 20% capacitor (Cc) is required between pins 48 and 50. If a polarized capacitor is used, the positive terminal must be connected to pin 48. The voltage rating of Cc must be 2x the maximum value of VCC.
1 V UA V UB V UC V LA V LB V LC V Sd V OA 2 3 4 5 6 7 8 9 10 11 12 13
I motor rms =
7A - 7A (7A - 3A) +
2
(7A - 3A) 3
2
20us 40us
Pc = (3.63 A)2 x (0.13 W) Pc = 1.71 Watts 2. Switching Losses (Ps) Ps = [ Vcc ( IOA (ts1) + IOB (ts2) ) fo] / 2 Ps = [ 28 V ( 3 A (325 ns) + 7 A (325 ns) ) 25 kHz] / 2 Ps = 1.14 Watts
14
15
16
17
18
19
1 0 1 0 1 0 1 0 1 0 1 0 1 0
H Z L H Z L H Z L
V Sd
1 0 H Z L
tSd
V OA
V OB V OC
FIGURE 5. SHUT-DOWN (VSd) TIMING RELATIONSHIPS
6
+VCC CC
48 INPUT COMMANDS 8 10 14 16 21 23 VUA VLA VUB VLB VUC VLC
50
32
39
46 V+ VLPI VO A 4 6 43,44,45 36,37,38 29,30,31
+ 15V
+CAP -CAP VCC A VCC B VCC A
COMMUTATION LOGIC
PWR-82330
VO B VO C
MOTOR
CURRENT SENSE CIRCUITRY
12
VSd VSS C VSS B
5,18,19 GND VSS A
26 27 28 33 34 35 40 41 42
RSENSE
FIGURE 6. FUNCTIONAL SHUT-DOWN INPUT USED WITH CURRENT-SENSING CIRCUITRY
3. Intrinsic Diode Losses (Pd) Pd= Id (avg) x Vd (avg) Id(avg) = [(IOB + IOA) / 2] / 2 = [(7 A + 3 A) / 2] / 2 = 2.5 A Pd = 2.5 A x 1.25 V Pd = 3.125 Watts
Permanent damage will result to the motor drive if the user does not make the following recommended ground connections that will ensure the proper operation of the hybrid. The V+ and logic grounds are on pins 5,18, and 19 (GND). The Vss connections for the output stage are on pins 26-28, 33-35 and 40-42 (VSS). To prevent damage to the internal drive circuitry, the differential voltage between GND and VSS must not exceed 3 V max, dc or peak. This includes the combined voltage drop of the associated ground paths and the voltage drop across Rsense (see FIGURE 9). For example, a value for Rsense of 0.1 will give a voltage drop of 1.00 V at 10 A and allow enough margin for the voltage drop in the ground conductors. Locate Rsense 1" - 2" maximum from the hybrid. It is critical that all ground connections be as short, and of lowest impedance, as the system allows. C1, C2, and C3 are 0.1 F ceramic bypass capacitors that supply high frequency spiking. The voltage rating should be 2x the maximum system voltage. These capacitors should be located as close to the hybrid as possible. Please note, on FIGURE 9, that C1, C2, and C3 must go directly from terminal-to-terminal on the hybrid - do not daisy chain along the power ground return. C4 and C5 are 0.01 F, 50 V ceramic capacitors for power supply decoupling. Locate as close to the hybrid as possible. CC is a 1 F, 20% capacitor (either polarized or nonpolarized). If a polarized cap is used, the positive terminal must be connected to pin 48 of the hybrid. Voltage rating should be 2x the maximum system voltage. Care must be taken to control the regenerative energy produced by the motor in order to prevent excessive voltage spiking on the VCC line. Accomplish this by placing a capacitor or clamping diode between VCC and high power ground return.
TRANSISTOR POWER DISSIPATION ( PQ)
To calculate the maximum power dissipation of the output transistor as a function of the case temperature use the following equation. (Reference FIGURE 8 to ensure you don't exceed the maximum allowable power dissipation of each transistor. PQ = Pc + Ps + Pd
TOTAL HYBRID POWER DISSIPATION (PTOTAL)
To calculate Total Power dissipated in the hybrid use: 6 PTOTAL= [ PQi ] where i = each transistor i=1
LAYOUT AND EXTERNAL COMPONENTS
Important Information - The following layout guidelines and required external components are critical to the proper operation of these motor drives.
7
SWITCHING LOSSES
ton VCC IOA IOB
IO ts1 t s2
FIGURE 7. OUTPUT CHARACTERISTICS
5.5 5.0
OUTPUT CURRENT, IO (amps)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -55 30 40 50 60 70 80 90 100 110 120 130
CASE TEMPERATURE, TC (C)
FIGURE 8. MAXIMUM ALLOWABLE CONDITIONS OUTPUT CURRENT VS. CASE TEMPERATURE
VCC 8 10 5
GND
VUA VLA
VCC A 46 VSS A VO A VCC B PWR-82330 VSS B VO B 36,37,38 32 26,27,28 29,30,31
C3
40,41,42 43,44,45 39 33,34,35
C1
14 16 18
VUB VLB
GND
C2
21 23 19
VUC VLC
GND V+ +CAP -CAP
VCC C VSS C VO C VLPI 6
C5
4
C4
48
50
CC
RSENSE
C1,C2,and C3=0.01 F ceramic capacitors C4 and C5=0.01 F ceramic capacitors
FIGURE 9. GROUND CONNECTIONS
8
MOUNTING
TABLE 4. PIN ASSIGNMENTS
The PWR-82330 package is designed for direct insertion to a printed wiring board. The heat transfer in a hybrid is from semiconductor junction to the bottom of the hybrid case. The flatness and maximum temperature of this mounting surface are critical to the performance and reliability, because this is the only method of dissipating the power generated in the hybrid. Use a mounting surface flatness of 0.004 inches/inch maximum. This interface can be improved with the use of a thermal compound or pad.
PIN 1 2 3 4 5 6 7 8 9 10 11 12
FUNCTION N/C N/C N/C V+ GND VLPI N/C VUA N/C VLA N/C VSd N/C VUB N/C VLB N/C GND GND N/C VUC N/C VLC N/C N/C
PIN 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
FUNCTION -CAP N/C +CAP N/C VC VO VO VO VSS VSS VSS VCC VO VO VO VSS VSS VSS VCC VO VO VO VSS VSS VSS
A A A A A A A B B B B B B B C C C C C C C
1.4000.005 (35.560.127) 1.2000.010 (30.480.254) 25 26
0.250 MAX (6.35) 0.2500.010 (6.350.254)
13 14 15 16
2.6000.005 (66.040.127)
0.1000.005 TYP (2.540.127)
17 18 19 20
24 EQ. SP. @ 0.100=2.4000.010 (@ 2.54=60.960.254)
21 22 23
0.0180.002 DIA TYP (0.4570.051) 1 50 SIDE VIEW
24 25
PIN NO. 1 CONTRASTING COLOR BEAD
BOTTOM VIEW
NOTES: 1. DIMENSIONS IN INCHES(MM). TOL = 0.005(0.127). 2. LEAD CONCENTRATION NUMBERS ARE FOR REFERENCE ONLY.
FIGURE 10. MECHANICAL OUTLINE
9
ORDERING INFORMATION
PWR-82330-XX0X Supplemental Process Requirements: S = Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source and 100 Blank = None of the Above Process Requirements: 0 = Standard DDC Processing, no Burn-In (See table below.) 1 = MIL-PRF-38534 Compliant 2 = B* 3 = MIL-PRF-38534 Compliant with PIND Testing 4 = MIL-PRF-38534 Compliant with Solder Dip 5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip 6 = B* with PIND Testing 7 = B* with Solder Dip 8 = B* with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.) Temperature Grade/Data Requirements: 1 = -55C to +125C 2 = -40C to +85C 3 = 0C to +70C 4 = -55C to +125C with Variables Test Data 5 = -40C to +85C with Variables Test Data 8 = 0C to +70C with Variables Test Data *Standard DDC Processing with burn-in and full temperature test -- see table below.
STANDARD DDC PROCESSING MIL-STD-883 TEST METHOD(S) INSPECTION SEAL TEMPERATURE CYCLE CONSTANT ACCELERATION BURN-IN 2009, 2010, 2017, and 2032 1014 1010 2001 1015, Table 1 CONDITION(S) -- A and C C A --
10
NOTES
11
The information provided in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7420 Headquarters - Tel: (631) 567-5600 ext. 7420, Fax: (631) 567-7358 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com
ILC DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976
C-07/99-500
PRINTED IN THE U.S.A.
12

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